1. Technical Field
Various embodiments may generally relate to a semiconductor device, and, more particularly, to an address latch circuit, an address processing circuit and a semiconductor apparatus.
2. Related Art
The combination of reducing the size of semiconductor apparatuses along with increasing the processing speeds of the semiconductor devices leads to increasing error occurrence rates relating to writing or reading data processes.
To detect and correct such data error, an error correction circuit, i.e., an error check correction (ECC) circuit, is used.
The error correction circuit may generate a parity signal for a plurality of data to be written, correct an error for the plurality of data to be read according to the parity signal, and then output the data.
Therefore, an address for a normal data write operation and an address for an error correction operation require separate processing operations, thus causing an increase in the number of elements of a related circuit.